--Academic Qualification
--Research Experience
--Summary of Research Interests
--Research Statement
     (Note for DAIICT students interested in working on Neuromorphic hardware projects)
Teaching Publications

Conferences & Workshops Attended Other Professional Activities Researh Projects

Awards and Scholarships Personal Info Useful Links
        

Mazad S. Zaveri (Ph.D.)

Assistant Professor
Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT),
Near Indroda Circle,
Gandhinagar - 38200
7,
Gujarat, India

Office Location:    
Room No.4206,  Faculty Block - 4
Office Ph: 91-079-30510638
Office Time: M-F:  9 am to 6 pm
Office Hours: Check  my daily schedule

Email:
mazad_zaveri<AT>daiict <DOT>ac<DOT>in
DA-IICT on Google Maps

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© Mazad S. Zaveri (2010)
Last edited on 27-Jan-2011

Webpage Keywords:

Biologically-inspired, Bio-inspired, Brain, Cortex, Neuron, Cortical, Cortical column, Neural, spiking neurons, Neural networks (NN), Artificial neural networks (ANN), Synapse, Cortex-inspired, Visual cortex, BICA - Biologically inspired cognitive architectures, Neuromorphic, Neuro-inspired, Bayesian, Computational model, Pearl - Belief Propagation, hierarchical and modular intelligent systems, Bayesian memory, Palm associative memory, Bayesian inference, probabilistic framework, cortex-scale, mammalian cortex, learning, unsupervised training, HTM - Heirarchical temporal memory, Jeff Hawkins, Numenta, Intelligent signal processing - ISP, neural emulation, neural simulation, Bayesian vision, spiking neural networks, Artificial cortex, Artificial brain, Artificial electronic cortex

CMOS, VLSI, digital, mixed-signal, architecture, micro-architecture, CMOL, hybrid nanotechnology, nanoelectronics, nano-architecture, Vector-matrix multiplication, nanogrid, crossbar, nanowire, nano-device, nano-switch, circuit design, memristor, 1R1D, Field programmable nanowire interconnect - FPNI, virtualization spectrum, hardware design space, architecture assessment methodology, performance price investigation, Field programmable Bayesian Array - FABA, virtualization  - time multiplexing hardware resources,  hardware implementation, ITRS, morphic architectures, emerging research devices, emerging research architectures, DARPA SyNAPSE
















Useful Links

Webpages of researchers working on
Cortex-inspired or Neuromorphic hardware platforms, etc
Prof. Dan.Hammerstrom - The pioneer of CNAPS - one of the most well known commercially available SIMD neurocomputer (Connected Network of Adaptive Processors -CNAPS) used for various neural network simulation, image-processing, etc.
 
Prof. Carver Mead - The pioneer of "neuromorphic hardware" and "silicon retina", and the one who coined the term "neuromorphic" in the 80's

Prof .Anders Lansner - He leads the computational neuroscience platfrom at Stockholm Brain Insitute, and the Dept. of Computational Biology and Neurocomputing at KTH Royal Institute of Technology, Sweden

Prof. Henry Markram - He leads the IBM/EPFL Blue Brain Project, at Ecole Polytechnique Federale de Lausanne, Switzerland

Prof . Kwabena Boahen - He leads the Brains on Silicon group at Stanford University

Prof. Gert Cauwenberghs - Works on the digital and analog VLSI microsystems for adaptive neural computations and sensory information processing.

Dr. Dharmendra Modha - Leads the Cognitive Computing Division at IBM Almaden Research Center, and principal investigator of DARPA's SyNAPSE program

Prof. Konstantin K. Likharev - The pioneer of hybrid nanoelectronic technology CMOL ( = CMOS stacked with a layer of perpendicular nanowire grids with nanodevices at each crosspoint in the grid)

Prof. Tarek Taha - Works on supercomputer and multi-FPGA systems for implementing and accelerating neocortex inspired computational models

Dr. Greg Snider - At HP labs, investigator of HP's FPNI (nano-memristor grid based FPGA architecture)
Jeff Hawkins, the founder of Numenta Inc. and the Redwood Neuroscience Institute, University of California, Berkeley Numenta is creating a new type of computing technology modeled on the structure and operation of the neocortex. The technology is called Hierarchical Temporal Memory, or HTM, and is applicable to a broad class of problems from machine vision, to fraud detection, to semantic analysis of text. HTM is based on a theory of neocortex first described in the book On Intelligence by Numenta co-founder Jeff Hawkins, and subsequently turned into a mathematical form by Numenta co-founder Dileep George.

Dr. Dileep George's PhD dissertation - "How the brain might work"
Most important research programs on Neuromorphic hardware systems
Useful datasets for pattern recognition Data for Matlab Hackers (by Prof. Sam Roweis)
MNIST Handwritten Character database (by Prof Yann LeCunn)




Career Profile

Academic Qualification

Ph.D. - Electrical and Computer Engineering (Dec. 2009)
Maseeh College of Engineering and Computer Science,
Portland State University, Portland, Oregon, USA
PhD Dissertation Title: CMOL/CMOS hardware architecture and performance/price for Bayesian memory - The building block of  intelligent systems
Dissertation Advisor: Prof. Dan Hammerstrom, Associate Dean, Maseeh College of Engineering and Computer Science, Portland State University
Disssertation Committee: Prof. Rob Daasch, Prof. Wu-Chi Feng, Prof. George Lendaris, Prof. Xiaoyu Song
PhD Dissertation abstract on ProQuest LLC (UMI® Dissertation Publishing) ISBN 9781109566826


M.S.E. - Electrical Engineering (May 2003)
(Specialization: CMOS Electronic Circuits)
Ira A. Fulton Schools of Engineering,
Arizona State University, Tempe, Arizona, USA

B.E. - Instrumentation and Control Engineering (Dec 2000)
Nirma Institute of Technology,
Gujarat University, Ahmedabad, Gujarat, India

Schools attended:
Little Flower School, Ahmedabad, Gujarat
St. Stephen's High School, Dahod, Gujarat
St. Xavier's High School, Loyola Hall, Ahmedabad, Gujarat

Research Experience

I have had the opportunity to work (as a research assistant) on various projects, related to neuromorphic and cortex-inspired algorithms and their hardware implementation and investigation, including CMOS and CMOL (hybrid nanotechnology) based digital and mixed-signal circuits and architectures. I have participated in the following projects: (Link to: Details of the following projects)
   

Research

Figure 1: Summary of Research Interests 

Research Interests  (Figure 1 summarizes my research interests)

Computational Models:
Electronic Hardware - Neuromorphic Circuits and Architecture (for the above computational models):

Figure 2: Hardware Design Space

Research Statement

The semiconductor/VLSI (electronics) industry has been following Moore’s Law since several decades, and has reaped tremendous benefits in terms of transistor speed and density. Transistor density on current state-of-the-art Intel microprocessors has reached billion/die, and transistor speeds are in pico-seconds. However, the semiconductor industry is now facing several challenges as the transistor scaling (according to Moore’s Law) approaches the lower nano-scale regime. In addition, so far, the computer industry has focused on only general-purpose processors/architectures. Some ultimate questions for the future of the computer engineering field are: How do we advance the field of computer engineering over the next few decades? And how do we efficiently utilize the currently available high density and speed advantages of semiconductor technology? Other than general-purpose computing, where else can we use computer technology?

 One proposed interim solution to the above challenges is the use of emerging nanoelectronic technologies, and in particular, hybrid nanotechnologies, such as CMOL. Of course, many of these nanotechnologies are currently in the development stage, and commercial mass production could take at least a decade. Another proposed “architectural solution” is the study of application-specific hardware architectures inspired from biological systems, such as the mammalian or human cortex, etc. Such application-specific hardware architectures/processors have primarily two functions, given as follows:

1) Mimic and/or morph some of the functionality of various parts of the cortex, by implementing the mathematical/computational models provided by the computational or “systems” neuroscientists1. This research/study is mostly intended to advance science, and learn more about how the human brain (cortex) functions, and how it achieves its emergent intelligent behavior.

2) Real-world large-scale (“intelligent signal-processing”) applications in computer vision, image and speech recognition, autonomous navigation/tracking, robotics, sensory/medical data collection, etc. This research/study has enormous commercial applicability and potential, for intelligent applications in embedded devices, such as hand-held devices, cell-phones, PC peripherals, etc.

 At the IEEE Centenary in 1984 (“The Next 100 Years,” IEEE Technical Convocation) Dr. Robert Noyce, co-founder of Intel and co-inventor of the Integrated Circuit, said: “Until now we have been going the other way; that is, in order to understand the brain we have used the computer as a model for it. Perhaps it is time to reverse this reasoning: to understand where we should go with the computer, we should look to the brain for some clues.

 My research concentrates on the study/investigation of (custom) application-specific hardware architectures that implement some of the sophisticated computational models of the visual cortex, provided by computational neuroscientists. This investigation focuses on the efficient use of current semiconductor technology and emerging nanotechnology candidates, particularly for implementing (computation and memory intensive) applications/models inspired from neurosciences. Special capabilities, such as the inherent (combined) storage and computation benefits, available from some of the emerging nanoelectronics provides a better match for implementing these biologically-inspired models, potentially providing several times better cost-performance over implementations that use traditional semiconductor technologies.

 According to Prof. Anders Lansner2, the ultimate goal3 of researchers (including myself) in the field of neuromorphic or biologically-inspired (electronic) hardware architectures is to “eventually build an ‘artificial electronic brain’ that is the same size as that of the human brain/cortex, operates faster than the brain, and consumes manageable power”. Of course, this goal sounds unfeasible for the next couple of decades, because it still requires enormous research by neuroscientists. However, to test some of the proposed theories/algorithms for the cortex, neuroscientists will require large-scale hardware platforms. As a result, a methodical exploration of the potential (neuromorphic) hardware platforms/architectures is warranted from the electronics/computer engineering perspective. Emerging nanoelectronic technologies, such as CMOL, have shown the potential for implementing mammalian cortex-scale systems, because these technologies will approach biological/cortical densities, have several times better performance, and consume manageable amounts of power.

 For the next few years, my research agenda would be to explore the hardware design space (investigate and compare these CMOS/Nano designs) for implementing the models/algorithms from computational neurosciences. My domain is mostly electronics and computer engineering; hence, to study/understand such algorithms, I would also require collaboration with the computer science faculty, working on computational models in machine learning/Artificial Intelligence (AI).

 What is the scope of such research in India?

In India, there is ongoing research in neurosciences, for example, at the National Institute of Brain Research (http://www.nbrc.ac.in/), a Govt. of India undertaking. However, research in computational neuroscience, especially from the perspective of real-world applications, seems to be scarce.

Research on neuromorphic or biologically-inspired hardware/VLSI is almost negligible in India. Hence, the domain of neuromorphic hardware/VLSI should provide ample of research opportunities in the future. And with the advent of novel nano-scale electronic devices/circuits, the prospects of research and development in the field of neuromorphic nano-scale hardware/VLSI, and in general, the application/utilization of nano-scale technology, are bright.   

 To summarize, all these efforts, to study and morph the mammalian cortex, are a part of the larger objective – “Reverse Engineering the Brain”, which is one of the 14 grand challenges of engineering (http://www.engineeringchallenges.org/), of the 21st Century, announced by the National Academy of Engineering of the U.S. National Academy of Sciences, in 2008.

1 Researchers have been studying the mammalian and human cortex, especially the visual cortex, since several decades. Cortex is considered as the “ultimate cognitive processor”, and there is no other better place to look for inspiration. Recently, the computational neuroscience community has started providing sophisticated computational models, which have tremendous potential for real world applications. For example, Numenta Inc.(http://www.numenta.com/) uses neocortex-inspired models for numerous real-world applications.

2 Prof. Anders Lansner leads the computational neuroscience platform at Stockholm Brain Institute (http://www.stockholmbrain.se/), and heads the Computational Biology and Neurocomputing department at the Royal Institute of Technology, Sweden.

3 In fact, the “SyNAPSE” program (http://www.darpa.mil/dso/thrusts/bio/biologically/synapse/index.htm) of the Defense Advanced Research Projects Agency (DARPA) of the U.S. Govt., which is currently in its first phase, is the most ambitious project so far on “Brain-on chip”, and it aims at building (artificial) mouse and cat cortex-scale hardware systems using a combination of current technology and emerging nanoelectronic technology (CMOL).

Note for DAIICT students - who wish to work on Neuromorphic circuits/hardware projects

It would be a good idea to read my research interests before meeting me regarding projects. Also, please read the following classical paper, which provides a simple survey of digital neuro hardware implementations and various aspects related to it.
H. Klar et al., 'Digital neuro hardware: principles and perspectives," Proc. of Neural Networks in Applications, Magdeburg, 1998. pp 101-106. [PDF]

Publications

Thesis/Dissertation

  1. M. S. Zaveri, "CMOL/CMOS hardware architecture and performance/price for Bayesian memory - The building block of  intelligent systems," PhD dissertation, Dept. of Electrical and Computer Engineering, Portland State University, Nov. 2009. ProQuest LLC (UMI® Dissertation Publishing) Publication Number: AAT 3391676, ISBN:  9781109566826  Preview the PDF

Journals

  1. M. S. Zaveri and D. Hammerstrom, “CMOL/CMOS implementations of Bayesian polytree inference: Digital & mixed-signal architectures and performance/price,” IEEE Transactions on Nanotechnology, vol. 9 (2), Mar. 2010. DOI 10.1109/TNANO.2009.2028342 [PDF]
  2. M. S. Zaveri and D. Hammerstrom, “Performance/Price Estimates for Cortex-Scale Hardware: A Design Space Exploration,” Neural Networks (Official Archival Journal of the International Neural Network Society, the European Neural Network Society, and the Japanese Neural Network Society), vol. 24, Apr. 2011. DOI 10.1016/j.neunet.2010.12.003

Conferences

  1. C.-H. Luk, M. S. Zaveri, D. Hammerstrom, and R. J. Kerr, “Vision-Based Hazard Detection,” paper presented in Conf. Artificial Neural Networks in Engineering, (St. Loius, MI), Nov. 2007 [PDF]
  2. C. Gao, M. S. Zaveri, and D. Hammerstrom, “CMOS / CMOL architectures for spiking cortical column,” in Proc. IEEE World Congress on Computational Intelligence – Int. Joint Conf. on Neural Networks, Hong Kong, June 2008, pp. 2442-2449. DOI 10.1109/IJCNN.2008.4634138 [PDF]   
  3. D. Hammerstrom and M. S. Zaveri, “Bayesian memory, a possible hardware building block for intelligent systems,” AAAI Fall Symposium Series on Biologically Inspired Cognitive Architectures (Arlington, VA), AAAI Press, Menlo Park, CA, TR FS-08-04, Nov. 2008, p. 81 [PDF]
  4. M. S. Zaveri and D. Hammerstrom, “Prospects for Building Cortex-Scale CMOL/CMOS Circuits: A Design Space Exploration,” IEEE Norchip Conference, Trondheim, Norway, Nov. 2009. DOI 10.1109/NORCHP.2009.5397858  [PDF]
  5. M. S. Zaveri, D. Voils, and D. Hammerstrom, “Using computational neuroscience to build better computers,” poster presented in The Science and Business of the Brain: Oregon Innovation Showcase, Portland, OR, Nov. 2009

Book Chapters/Sections

  1. C.-H. Luk, M. S. Zaveri, D. Hammerstrom, and R. J. Kerr, “Vision-Based Hazard Detection,” in Intelligent Engineering Systems Through Artificial Neural Networks: Smart Engineering System Design. Vol. 16, C. H. Dagli, A. L. Buczak, D. L. Enke, M. Embrechts, and O. Ersoy, Eds. NY: ASME Press, 2007, pp. 439-444 DOI  10.1115/1.802566.paper66  
  2.  M. S. Zaveri and D. Hammerstrom, “Chapter 4. CMOL/CMOS Implementations of Bayesian Inference Engine: Digital & Mixed-signal Architectures and Performance/price – A Hardware Design Space Exploration” in CMOS Nano-electronics: Processors and Memories, Kris Iniewski Ed., Springer:Germany, ISBN: 978-90-481-9215-1, Aug. 2010

Teaching

Autumn 2010, Autumn 2011

EL 511 VLSI Design   (M.Tech core course)

Winter 2011, Winter 2012 

EL114 Digital Logic Design (B.Tech core course)

Seminars/Workshops Attended

  1. Architectures for Silicon Nano-Electronics and Beyond: A Workshop to Chart Research Directions, Sponsored by National Science Foundation (NSF), (Portland, OR), Sept. 2005. Available: http://web.cecs.pdx.edu/~strom/nsf_workshop/nsf_workshop.html 
  2. A NeuroSilicon Workshop, Sponsored by Office of Naval Research (ONR), (Portland, OR), Aug. 2006. Available: http://web.cecs.pdx.edu/~strom/onr_workshop/onr_workshop.html 
  3. Conference on Artificial Neural Networks in Engineering (ANNIE), (St. Loius, MI), Nov. 2007. 
  4. Technology Maturity for Adaptive Massively Parallel Computing: A Workshop to Chart Architectural Readiness of Real-World Applications, Sponsored by Intel Corp., ONR, NSF, (Portland, OR), Mar. 2009. Available: http://www.technologydashboard.com/adaptivecomputing/
  5. Oregon Innovation Showcase: The Science and Business of the Brain, (Portland, OR), Nov. 2009. Available: http://icoregon.net/icoregon_showcase.html

Research Projects

Industry Research Projects

Talks are underway to collaborate with Future Digital Technologies - Ahmedabad , which is local company developing embedded hardware/software solutions.
Students interested in any projects/internships at Future Digital Technologies should check out the company's website, and then contact me.

Academic Research Projects (by B.Tech. and M.Tech. students) 

  1. B.Tech. Project - Verilog (parameterized) implementation of a (Spiking Neural Network) Processing Node, by Mayank Jain
  2. B.Tech. Project - Mixed-signal CMOS circuit implementation of  best-match Content Addressable Memory (CAM), by Akash Gupta
  3. M.Tech. Thesis - FPGA implementation of environment/noise classification and reduction using neural networks, by Nikita Ambasana
  4. M.Tech. Thesis - Investigation of Multi-FPGA (wireless/wired) architecture for mapping  (parameterized) Spiking Neural Network - Processing Nodes, by Sujit Chavada
  5. M.Tech. Thesis - Digital / Mixed-Signal CMOS circuit implementation of vector-matrix multiplication structures, by Vaibhav Chhaya


Other Professional Activities

Reviewer for articles from following Journals/Conferences/Symposiums

Program/Advisory Committee Member for following Conferences/Symposiums/Workshops/Associations



Awards and Scholarships


Personal Info

I Grew up in: Dahod (1985-1992), and Ahmedabad (1979-1985 and 1992-2001) in Gujarat State
I have stayed in the US: 2001-2010 (2 years in Tempe, AZ, and around 7 years in Portland, OR)
Hometown: Devgadh Baria, and Dahod (both in the Panchmahal/Dahod district)

Religion by birth: Zoroastrian - Parsi
Beliefs and Faiths: God fearing, believe in the Supreme Creator/God, monotheist, believe in astrology and the science behind it, believe in cosmic energy (e.g. energy of the pyramids in Egypt), believe in occult phenomena/sciences, believe in following Zoroastrian/Parsi customs and rituals, etc.

Like Pets or Animals: Yes (In the past, had a pet for 8 years)

Interests: Music, Movies, Driving and Automobiles, Animals, Engineering, Earth/Planet, Astrology, Road and Driver Safety, Religion, Culture, Fitness/Diet/Food, etc

TV Shows / Movies Genre: Comedy, Action, Suspense, Adventure, Courtroom Drama, Detective, Animals, Earth/Travel, Culture, Machines/Engineering/Manufacturing, etc

Political Views: None / Not Interested
Philosophical Views: None; willing to listen and evaluate new ideas
Personal Values: Honesty, Rationality, Moral and Ethical Integrity

Being a Leo...
Positive Traits of Leo: Generous, warmhearted, Creative, Enthusiastic, Broad-minded, Faithful, Loving
Negative Traits of Leo: Pompous and patronizing, Bossy and interfering, Dogmatic and intolerant